This invention relates generally to power-on reset circuits and specifically to a power-on reset circuit that is asserted at different voltage levels depending on whether or not the circuit has already become operational.
Power-on reset circuits are commonplace in digital circuit designs. The power-on reset (POR) signal, or merely reset signal, is useful to place the circuit being controlled by the POR signal into a known state after power has first been applied to the circuit. This is especially useful in circuits that use storage elements since the state of a storage element is undefined shortly after power is turned on thus placing the circuit in an unknown and potentially dangerous state.
An example of a power-on reset circuit is U.S. Pat. No. 5,243,233 by Cliff. Cliff discloses a power-on reset circuit where storage elements such as SRAM cells are formed in an integrated circuit. In order to insure that the reset signal is asserted until the SRAM cells become operational, Cliff uses a representative SRAM cell in the generation of the reset signal. The SRAM cell used in the generation of the power-on reset signal is representative of other SRAM cells fabricated on the same silicon substrate forming the integrated circuit. In other words, the SRAM cell and the power-on reset circuit have the same process characteristics as the rest of the cells in the integrated circuit.
The use of identical process storage elements in the POR circuit allows the Cliff POR circuit to deassert the reset signal just after the SRAM cells in a circuit being controlled by, or receiving, the POR signal are known to be operational. This, in turn, reduces the necessary safety margin incorporated in the generation of a reset signal to ensure that storage elements are fully operational before deasserting the reset signal. By reducing the safety margin the reset signal is deasserted earlier in time and the controlled circuit may begin operation earlier than with other forms of reset signal circuits.
However, a problem exists with power-on reset circuits such as Cliff and the prior art in that once the circuit has become operational, a slight decrease in the power supply voltage level may cause the power-on reset circuitry to again assert the reset signal even though such assertion may not be necessary. For a digital system, the assertion of the reset signal when it is not absolutely necessary, results in an interruption of the performance of the digital circuit and, depending the application, could be a very undesirable event.
Thus, it is desirable to have a power-on reset circuit that prevents the reassertion of the reset signal unless it is absolutely necessary.